400G IPU Case Study: Demonstrating Shift-left of Soft Logic RTL Development on Real World Design using Intel Agilex FPGA SystemC Model
Pravat Kishor Nayak¹; Vikrant Kapila²; Pushpa Naik¹; Niketkumar Natvarbhai Sharma¹
¹ Intel Technology India Pvt Ltd; ² Intel Technology Asia Pte Ltd
A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural Networks
Youssef Maher Nader¹; Mostafa Lotfy Hatab¹; Mazen Mostafa Ghaleb¹; Safia Medhat Bakr¹; Tasneem A. Awaad¹; Ahmed AlGanzouri²; Dr. Mohamed Abdelsalam²; Prof. Dr. M. Watheq El-Kharashi¹
¹ Faculty of Engineering, Ain Shams University; ² Siemens EDA
A Hybrid Approach For Interrupts Verification
Dr. Giovanni Auditore MdB¹; Dr. Qibo Peng MdB²; Dr. Francesco Rua’ MdB¹
¹ STMicroelectronics srl; ² Politecnico di Torino
A Model-Based Reusable Framework to Parallelize Hardware and Software Development
Tom Richter¹; Jouni Sillanpää²; Hakan Pettersson¹
¹ MathWorks; ² Nokia
A Novel Approach to Standardise Verification Configurations using YAML
Nikhil Tambekar
Nokia Solutions and Networks Oy
A Novel Framework to Accelerate System Validation on Emulation
Sarang Madhukarrao Kalbande¹; Rinkesh Yadav¹; Sarang Kalbande¹; Garima Srivastava¹; Hyundon Kim²
¹ Samsung Semiconductor India R & D Centre(SSIR); ² Samsung Electronics, Korea
A perfect blend of verification techniques, platforms, and AI-empowered debugging in Ethernet Subsystem Verification
Tijana Misic; Olivera Stojanovic
Vtool doo
A scalableVIP component to increase robstuness of co-verification within an ASIC
Mario de Matteis; Matteo Barbati
ON Semiconductor
A tool for Investigating Cyber-Physical Systems via SystemC AMS Virtual Prototypes Derived from SysML Models
Dr. Daniela Genius¹; Prof. Ludovic Apvrille²
¹ Sorbonne Université – LIP6; ² Télécom Paris, Institut Polytechnique de Paris
A UVM Test-bench Skeleton Leveraging the Event Pool and Sequence Layering
Marcela Zachariasova PhD¹; Tomáš Pehnelt; Jiri Bartak; Jan Riha
¹ ASICentrum, EM Microelectronic
Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection
Jakub Pluciński¹; Łukasz Bielecki¹; Robert Synoczek¹; Emelie Andersson²; Antti Löytynoja²; Cristian Macario²
¹ Nokia; ² MathWorks
Accelerating Complex System Simulation using Parallel SystemC and FPGAs
Stanislaw Kaushanski¹; Johannes Wirth²; Eyck Jentzsch¹; Andreas Koch²
¹ MINRES Technologies GmbH; ² Technische Universität Darmstadt
An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective
Chakravarthi Devakinanda Vurukutla¹; Sahana Ranganathan; Devendra Satish Bilaye; Vivek Kumar; Karthik Majeti
¹ Samsung Semiconductor India Research
An Improved Methodology for Debugging UPF Issues at SoC level Power Aware Simulations
Ruchi Misra; Shrinidhi Rao; Alok Kumar; Garima Srivastava
Samsung Semiconductor India R & D Centre(SSIR)
Break the SoC with UVM Dynamically Generated Program Code
Bogdan Todea; Madhukar Mahadevappa
Microchip Technology
Bridging the gap between system-level and chip-level performance optimization
Soniya Gupta¹; Vikrant Kapila²; Holger Keding³; Tim Kogel³
¹ Synopsys India Pvt. Ltd.; ² Intel Inc (Singapore); ³ Synopsys Inc Achen Germany
Clock Tree Design Considerations in The Presence of Asymmetric Transistor Aging
Prof. Dr. Freddy Gabbay PhD¹; Firas Ramadan²; Majd Ganaiem²
¹ Ruppin Academic Center, Israel; ² Technion – Israel Institute of Technology
Closed-Loop Model-First SoC Development With the Intel Simics Simulator
Kalen Brunham; Anthony Moore; Tobias Rozario; Wei Jun Yeap; PhD Jakob Engblom
Intel Corporation
Co-Design of Automotive Boardnet Topology and Architecture
Sebastian Post; Prof. Dr. Christoph Grimm
Control Flow Analysis for Bottom-up Portable Models Creation
Petr Bardonek; Marcela Zachariášová PhD
Brno University of Technology, Faculty of Information Technology
Design Verification of the Quantum Control Stack
Samin Ishtiaq; Rojalin Mishra; Dr. Seyed Amir Alavi PhD; Dr. Nick Johnson; Dwaraka O N; Asher Pearl
Riverlane
DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VPs
Christoph Hazott MSc.; Prof. Dr. Daniel Große
Johannes Kepler Universitaet Linz
Effective Design Verification – Constrained Random with Python and Cocotb
Suruchi Kumari¹; Deepak Narayan Gadde
¹ Infineon
Efficient Debugging on Virtual Prototype using Reverse Engineering Method
Sandeep Puttappa; Dineshkumar Selvaraj; Ankit Kumar
Infineon Technologies
Efficient Verification of a RADAR SoC Using Formal and Simulation-Based Methods
Aman Kumar¹; Mark Litterick²; Samuele Candido¹
¹ Infineon Technologies Dresden GmbH & Co. KG; ² Verilab GmbH
Evaluation of the RISC-V Floating Point Extensions
Niko Zurstraßen¹; Lennart Michael Reimann¹; Nils Bosbach¹; Lukas Jünger²; Rainer Leupers¹
¹ RWTH Aachen University; ² MachineWare GmbH
Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive Applications
Dr. Mohammad Badawi PhD; Javier Castillo; Dr. Andreas Mauderer PhD; Dr. Jan-Hendrik Oetjens
Robert Bosch GmbH
Fuzzing Firmware running on Intel® Simics® Virtual Platforms
PhD Jakob Engblom; Dr. Robert Guenzel
Intel Corporation
Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor
Dr. Claudio Raccomandato¹; Prof. Emad Arasteh²; Prof. Rainer Dömer²
¹ Politecnico di Torino; ² University of California, Irvine
HW-SW-Coverification as part of CI/CD
Johannes Grinschgl¹; Ganesh Rajasekharan Nair²; Alexander Hoffmann³; Nan Ni
¹ Infineon Technologies AG, Neubiberg, Germany; ² Infineon Technologies AG Neubiberg, Germany ; ³ Infineon Technologies AG
Hybrid Emulation for faster Android Home screen bring up and Software Development
Sarang Kalbande¹; Manoj Khandelwal¹; Sarang Kalbande¹; Garima Srivastava¹; Hyundon Kim²
¹ Samsung Semiconductor India R & D Centre(SSIR); ² Samsung Electronics, Korea
Initialization Techniques for D-Flip-Flop Based Scan Chain with Scan Flush Architecture in Gate-Level Simulation
Wei Jun Yeap, Programmable Solutions Group, Intel, Penang, Malaysia
Rahul Chauhan, Programmable Solutions Group, Intel, Bangalore, India
Wonyoung Choi, Programmable Solutions Group, Intel, Munich, Germany
Integration Verification of Safety Components in Automotive Chip Modules
Dr. Holger Busch
Infineon Technologies
Large-scale Gatelevel Optimization Leveraging Property Checking
Lucas Klemmer MSc.; Dominik Bonora; Univ.-Prof. Dr Daniel Große
Johannes Kepler University Linz
Low-Power Validation Framework for Standard Cell Library including Front-End and Back-End implementation
Jinho Lee¹; Hyunju Bak¹; SangGi Do¹; Taejun Yoo¹; Gowrishankar Srinivasan²; Vishw Mitra Singh Bhadouria²
¹ Samsung Electronics; ² Samsung Semiconductor India R & D Centre(SSIR)
MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells
Dr. Claudio Raccomandato¹; Prof. Emad Malekzadeh Arasteh²; Prof. Rainer Dömer²
¹ Politecnico di Torino; ² University of California, Irvine
MetaPSS: An Automation Framework for Generation of Portable Stimulus Model
Jaimini Nagar¹; Thorsten Dworzak²; Sebastian Simon¹; Ulrich Heinkel³; Djones Lettnin²
¹ Infineon Technologies Dresden GmbH & Co. KG; ² Infineon Technologies AG Munich; ³ Technical University Chemnitz
On the Performance Differences of SystemC and SystemC AMS: A Guideline for Real Number Modeling and Beyond
Alexandra Küster¹; Dr. Rainer Dorsch¹; Prof. Dr. Christian Haubelt ssdd²
¹ Bosch Sensortec GmbH; ² University of Rostock
Planning for RISC-V Success: Verification Planning and Functional Coverage lead to quality RISC-V processor IP
Aimee Sutton¹; Duncan Graham¹; Simon Davidmann¹; Pascal Gouedo²; Yoann Pruvost²; Xavier Aubert²
¹ Imperas Software Ltd.; ² Dolphin Design
Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level Integration
Tchiya Dayan
Mobileye
Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)
Aman Kumar¹; Muhammad Ul Haque Khan²; Bijitendra Mittra²
¹ Infineon Technologies Dresden GmbH & Co. KG; ² Cadence Design Systems
Reverse Hypervisor – Faster SoC Simulation, an approach to Arm on Arm on Arm
François-Frédéric Ozog¹; Mark Burton²
¹ Shokubai.tech; ² QUALCOMM
Self-Triggering Mechanism for Modeling a Low-Dropout Regulator with Load Capacitor
Mariska van der Struijk; Yi Wang
Renesas Electronics Cooperation
Smart TSV (Thru Silicon Via) Repair Automation in 3DIC designs
Subramanian R; Jyoti Verma; Naveen Srivastava; Sekhar Dangudubiyyam
Samsung Semiconductor India R & D Centre(SSIR)
SV VQC UDN for Modeling Switch-Capacitor-based Circuits
PhD Yi Wang
Renesas Electronics Cooperation
System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog
Seungah Park¹; Dr. Hyeongseok Seo²; Dr. Canxing Piao²; Jaemin Park³; Prof. Jaehyuk Choi⁴; Prof. Jung-Hoon Chun⁴
¹ Sungkyunkwan University (SKKU); ² SolidVue Inc.; ³ Scientific Analog Inc.; ⁴ Sungkyunkwan University (SKKU), SolidVue Inc.
Testbench Linting – open-source way
Srinivasan Venkataramanan¹; Deepa Palaniappan¹; Satinder Paul Singh²
¹ AsFigo Technologies; ² Cogknit EU
The Road to Robustness: Addressing LPDDR5X PHY Verification Challenges with DFE
Chethan Gowdra Bomanna; Muhammed Asif Kavil Thodukayil; Anil Deshpande
Samsung Semiconductor India R & D Centre(SSIR)
The Three Body Problem
Peter Birch¹; Ben Marshall²
¹ VyperCore; ² PQShield
Towards a Hybrid Verification Environment for Signal Processing SoCs
Jan Hahlbeck; Steffen Löbel; Chandana G.P.
NXP Semiconductors Germany GmbH
Unified Architecture of L1 and L2 Cache with Low Power Extensions for Multi-Core UVM-based Library Package
Avnita Pal; Priyanka Gharat; Sastry Puranapanda; Darshan Sarode
Silicon Interfaces
Variation-Aware Performance Verification of Analog Mixed-Signal Systems
Dr.-Ing. Carna Zivkovic¹; Jan Rödel²; Neha Chavan²; Prof. Dr. Christoph Grimm³; Frank Rethmeier²
¹ NXP Semiconductors; ² NXP Semiconductors Germany GmbH; ³ RPTU Rheinland-Pfälzische Technische Universität
Verification Methodology for Efficient PVT(Process, Voltage and Temperature)Variation Analysis & Characterisation for Thermal and Power Aggressor IPs in a 3D SOC.
Jasobanta Sahoo Jaso; Vineeth Rao Vineeth; Sekhar DANGUDUBIYYAM
Samsung Semiconductor India R & D Centre(SSIR)
Verification of an AXI cache controller using multi-thread approach based on OOP design patterns
Dr. Francesco Rua’ MdB¹; Péter Sági²
¹ STMicroelectronics srl; ² Veriest Solutions
Verilator + UVM-SystemC: a match made in heaven
Luca Sasselli
Qualcomm
Virtual ECUs with QEMU and SystemC TLM-2.0
Lukas Jünger¹; Dr. Jan Henrik Weinstock¹; Munish Jassi²; Hitoshi Hamao³; Megumi Yoshinaga³; Koichi Sato³
¹ MachineWare GmbH; ² Renesas Electronics Europe GmbH; ³ Renesas Electronics Corporation
Virtual testing of overtemperature protection algorithms in automotive smart fuses
Thomas Markwirth¹; Gabriel Pachiana¹; Dr. Christoph Sohrmann¹; Mehdi Meddeb²; Gunnar Bublitz²; Heinz Wagensonner²
¹ Fraunhofer IIS/EAS; ² CARIAD SE (Volkswagen Group)
VPSim : Virtual Prototyping Simulator with best accuracy & execution time trade-off for High Performance Computing systems evaluation and benchmarking
Ayoub Mouhagir; Mohamed Benazouz PhD; Lilia Zaourar PhD
CEA
