Exhibit Floor Open

T1.1

IP-XACT Tutorial

T2.1

Accellera Functional Safety Working Group Update and Next Steps

T3.1

Scalable agile processor verification using SystemC UVM friends

T4.1

SysML v2: An overview with demonstration

T1.2

AI-Driven Debug and Verification Management

T2.2

Shift your HDL design left and keep your eyes on team code metrics in FPGA & ASIC design and verification

T3.2

Model-Based Approach for Developing Optimal HW/SW Architectures for AI systems

T4.2

New Methods in Core and SoC Verification based on RISC-V

T1.3

IP-XACT Industrial Practices

T2.3

Migrating from UVM to UVM-MS

T3.3

Making the impossible possible: CDC and RDC closure with abstracts from different tools

T4.3

Open-Source Virtual Platforms for Industry and Research 

T1.4

How to leverage the power of MATLAB from Functional Verification Test Benches

T2.4

The Expanding role of Static Signoff in Verification Coverage

T3.4

Exploring New Frontiers of High-Performance Verification with UVM-AMS

T4.4

Double Software Verification Shift-left by combining Model-Based Design and Virtual ECUs’

Exhibit Floor Open

P1.1 

A Hybrid Approach For Interrupts Verification

Verification of an AXI cache controller using multi-thread approach based on OOP design patterns

[Short] Hybrid Emulation for faster Android Home screen bring up and Software Development

[Short] A perfect blend of verification techniques, platforms, and AI-empowered debugging in Ethernet Subsystem Verification

P2.1

SV VQC UDN for Modeling Switch-Capacitor-based Circuits

Self-Triggering Mechanism for Modeling a Low-Dropout Regulator with Load Capacitor

**[Short] On the Performance Differences of SystemC and SystemC AMS: A Guideline for Real Number Modeling and Beyond

**[Short] A tool for Investigating Cyber-Physical Systems via SystemC AMS Virtual Prototypes Derived from SysML Models

P3.1

[Short] A Model-Based Reusable Framework to Parallelize Hardware and Software Development

Fuzzing Firmware running on Intel® Simics® Virtual Platforms

[Short] 400G IPU Case Study: Demonstrating Shift-left of Soft Logic RTL Development on Real World Design using Intel Agilex FPGA SystemC Model

**Co-Design of Automotive Boardnet Topology and Architecture

P4.1

Verilator + UVM-SystemC: a match made in heaven

Closed-Loop Model-First SoC Development With the Intel Simics Simulator

** [Short] A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural Networks

** [Short] Large-scale Gatelevel Optimization Leveraging Property Checking

P5.1

[Short] An Improved Methodology for Debugging UPF Issues at SoC level Power Aware Simulations

Unified Architecture of L1 and L2 Cache with Low Power Extensions for Multi-Core UVM-based Library Package

Virtual testing of overtemperature protection algorithms in automotive smart fuses

[Short] Efficient Verification of a RADAR SoC Using Formal and Simulation-Based Methods

P1.2

A scalable VIP component to increase robstuness of co-verification within an ASIC

A Novel Framework to Accelerate System Validation on Emulation

[Short] Low-Power Validation Framework for Standard Cell Library including Front-End and Back-End implementation

[Short] Initialization Techniques for D-Flip-Flop Based Scan Chain with Scan Flush Architecture in Gate-Level Simulation

P2.2

System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog

**Clock Tree Design Considerations in The Presence of Asymmetric Transistor Aging

**Variation-Aware Performance Verification of Analog Mixed-Signal Systems

P3.2

[Short] Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive Applications

HW-SW-Coverification as part of CI/CD

Integration Verification of Safety Components in Automotive Chip Modules

[Short] Virtual ECUs with QEMU and SystemC TLM-2.0

P4.2

Accelerating Complex System Simulation using Parallel SystemC and FPGAs

** [Short] 
Design Verification of the Quantum Control Stack

Control Flow Analysis for Bottom-up Portable Models Creation

** [Short] MetaPSS: An Automation Framework for Generation of Portable Stimulus Model

P5.2

Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection

A UVM Test-bench Skeleton Leveraging the Event Pool and Sequence Layering

Towards a Hybrid Verification Environment for Signal Processing SoCs

P1.3

The Three Body Problem

Break the SoC with UVM Dynamically Generated Program Code

P2.3

Bridging the gap between system-level and chip-level performance optimization

**MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells

P3.3

Reverse Hypervisor – Faster SoC Simulation, an approach to Arm on Arm on Arm

Efficient Debugging on Virtual Prototype using Reverse Engineering Method

P4.3

Verification Methodology for Efficient PVT(Process, Voltage and Temperature)Variation Analysis & Characterisation for Thermal and Power Aggressor IPs in a 3D SOC.

Smart TSV (Thru Silicon Via) Repair Automation in 3DIC designs

P5.3

Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level Integration

The Road to Robustness: Addressing LPDDR5X PHY Verification Challenges with DFE

P1.4

Planning for RISC-V Success: Verification Planning and Functional Coverage lead to quality RISC-V processor IP

A Novel Approach to Standardise Verification Configurations using YAML

P2.4

**Evaluation of the RISC-V Floating Point Extensions

**DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VPs

P3.4

Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor

VPSim : Virtual Prototyping Simulator with best accuracy & execution time trade-off for High Performance Computing systems evaluation and benchmarking

P4.4

Testbench Linting – open-source way

Effective Design Verification – Constrained Random with Python and Cocotb

P5.4

An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective

Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)