Machine Learning for Coverage Analysis in Design Verification
Jayasree Venkatesh      
Qualcomm India Private Limited

SimPy and Chips: A Discrete Event Simulation Framework in Python for Large Scale Architectual Modelling of Machine Intelligence Accelerators
Daniel Wilkinson¹; Hachem Yassine¹; Graham Cunningham; Iason Myttas¹
¹ Graphcore Ltd

Optimizing Design Verification using Machine Learning: Doing better than Random
William Hughes, Maithilee Kulkarni, Sandeep Srinivasan, Rohit Suvarna
Verifai Inc

Achieving Faster Code Coverage Closure using High-Level Synthesis
Surendhar Thudukuchi Chandrapandiyan; PhD Preetham Lakshmikanthan; Ashwani Aggarwal; Youngchan Lee; PhD Youngsik Kim; PhD Seonil Brian Choi        
Samsung Electronics

Detection of Glitch-Prone Clock and Reset Propagation with Automated Formal Analysis
Kaushal Shah; Sulabh kumar Khare
Siemens Digital Industries Software

Using HLS to Improve Design-for-Verification of Multi-pipeline Designs with Resource Sharing
Sarmad Dahir; Nils Luetke-Steinhorst; PhD Christian Sauer          
Cadence Design Systems

Bringing Reset Domains and Power Domains Together – Set/Reset Flops Augmenting Complexities in Power-Aware RDC Verification
Manjunatha Srinivas¹; Manish Bhati¹; Abdul Moyeen¹; Inayat Ali² 
¹ Siemens Digital Industries Software; ² NXP Semiconductors

A Methodology for Evaluating SI Artefacts in DDR4-3DS PHY using Channel Modelling
Aditya S Kumar; Gowdra Bomanna Chethan; Shivani Maurya; Anil Deshpande; Somasunder Kattepura Sreenath
Samsung Semiconductor India R & D Centre(SSIR)

Using Dependency Injection Design Pattern in Power Aware Tests
Mehmet Tukel¹; Luca Sasselli; David Guthrie       
¹ QUALCOMM Ireland

Method for Early Performance Verification of Hardware-accelerated Embedded Processor Systems in RTL Simulation
Luca Sasselli¹; Mehmet Tukel; David Guthrie       
¹ Qualcomm

System-Level Register Verification and Debug
Utkarsh Bhiogade¹; Kautilya Joshi¹; Puneet Goel²
¹ Indian Institute of Information Technology Nagpur; ² Coverify Systems Technology

No Country for Old Men – A Modern Take on Metrics Driven Verification
Svetlomir Hristozkov; PhD James Pallister; Richard Porter    
Graphcore Ltd

A Novel Approach to Reuse Firmware for Verification of Controller Based Sub-Systems Using PSS
Vishnu Ramadas; Simranjit Singh¹; Ashwani Aggarwal; Woojoo Space Kim²; Seonil Brian Choi²         
¹ Samsung Semiconductor India R&D; ² Samsung Electronics

Reuse of System-Level Verification Components within Chip-Level UVM Environments
Diego Alagna¹; Marzia Annovazzi¹; Alessandro Cannone¹; Marcello Raimondi¹; Simone Saracino¹; Mukesh Chugh²; Marc Erickson²; Cristian Macario²; Giuseppe Ridinò²  
¹ STMicroelectronics; ² MathWorks

A Novel Approach to Functional Test Development and Execution using High-Speed IO
Marcus Schulze Westenhorst¹; Jörg Simon²; Markus Bücker¹; Klaus-Dieter Hilliges¹; Michael Braun¹ 
¹ Advantest Europe GmbH; ² Cadence Design Systems

Testbench Flexibility as a Foundation for Success
Ana Sanz Carretero¹; Katherine Garden; WeiWei Cheong
¹ Xilinx

Handling Asynchronous Reset(s) Testing by Building Reset-awareness into UVM Testbench Components
Wei Wei Cheong; Katherine Garden; Ana Sanz Carretero 
Xilinx Inc.

One Testbench to Rule Them All!
Salman Tanvir; Markus Brosch; Amer Siddiqi

A Comparison of Methodologies to Simulate Mixed-signal IC
Simone Fontanesi¹; Paul Ehrlich²; Karsten Einwich²; Gaetano Formato¹; Andrea Possemato¹
¹ Infineon Technologies Austria AG; ² COSEDA Technologies GmbH

Unified Model/Hardware-in-the-Loop Methodology for Mixed-Signal System Design and Hardware Prototyping
Martin Barnasconi¹; Wil Kitzen¹; Thieu Lammers¹; Paul Ehrlich²; Karsten Einwich²   
¹ NXP Semiconductors; ² COSEDA Technologies GmbH

Accelerated Coverage Closure by Utilizing Local Structure in the RTL Code
Gokce Sarar¹; Guillaume Shippee¹; Tushit Jain¹; Rhys Buggy²; Vishal Karna¹; Han Nuon¹    
¹ Qualcomm Technologies, Inc.; ² QT Technologies Ireland Limited

Machine Learning based Structure Recognition in Analog Schematics for Constraints Generation
Rituj Patel; PhD Husni Habal; Venkata Konda Reddy Rolla

Democratizing Formal Verification
Tobias Ludwig  
Lubis EDA

Netlist Paths: A Tool for Front-end Netlist Analysis
PhD Jamie Hanlon; Samuel Kong
Graphcore Ltd