Machine Learning for Coverage Analysis in Design Verification
Jayasree Venkatesh
Qualcomm India Private Limited
SimPy and Chips: A Discrete Event Simulation Framework in Python for Large Scale Architectual Modelling of Machine Intelligence Accelerators
Daniel Wilkinson¹; Hachem Yassine¹; Graham Cunningham; Iason Myttas¹
¹ Graphcore Ltd
Optimizing Design Verification using Machine Learning: Doing better than Random
William Hughes, Maithilee Kulkarni, Sandeep Srinivasan, Rohit Suvarna
Verifai Inc
Achieving Faster Code Coverage Closure using High-Level Synthesis
Surendhar Thudukuchi Chandrapandiyan; PhD Preetham Lakshmikanthan; Ashwani Aggarwal; Youngchan Lee; PhD Youngsik Kim; PhD Seonil Brian Choi
Samsung Electronics
Detection of Glitch-Prone Clock and Reset Propagation with Automated Formal Analysis
Kaushal Shah; Sulabh kumar Khare
Siemens Digital Industries Software
Using HLS to Improve Design-for-Verification of Multi-pipeline Designs with Resource Sharing
Sarmad Dahir; Nils Luetke-Steinhorst; PhD Christian Sauer
Cadence Design Systems
Bringing Reset Domains and Power Domains Together – Set/Reset Flops Augmenting Complexities in Power-Aware RDC Verification
Manjunatha Srinivas¹; Manish Bhati¹; Abdul Moyeen¹; Inayat Ali²
¹ Siemens Digital Industries Software; ² NXP Semiconductors
A Methodology for Evaluating SI Artefacts in DDR4-3DS PHY using Channel Modelling
Aditya S Kumar; Gowdra Bomanna Chethan; Shivani Maurya; Anil Deshpande; Somasunder Kattepura Sreenath
Samsung Semiconductor India R & D Centre(SSIR)
Using Dependency Injection Design Pattern in Power Aware Tests
Mehmet Tukel¹; Luca Sasselli; David Guthrie
¹ QUALCOMM Ireland
Method for Early Performance Verification of Hardware-accelerated Embedded Processor Systems in RTL Simulation
Luca Sasselli¹; Mehmet Tukel; David Guthrie
¹ Qualcomm
System-Level Register Verification and Debug
Utkarsh Bhiogade¹; Kautilya Joshi¹; Puneet Goel²
¹ Indian Institute of Information Technology Nagpur; ² Coverify Systems Technology
No Country for Old Men – A Modern Take on Metrics Driven Verification
Svetlomir Hristozkov; PhD James Pallister; Richard Porter
Graphcore Ltd
A Novel Approach to Reuse Firmware for Verification of Controller Based Sub-Systems Using PSS
Vishnu Ramadas; Simranjit Singh¹; Ashwani Aggarwal; Woojoo Space Kim²; Seonil Brian Choi²
¹ Samsung Semiconductor India R&D; ² Samsung Electronics
Reuse of System-Level Verification Components within Chip-Level UVM Environments
Diego Alagna¹; Marzia Annovazzi¹; Alessandro Cannone¹; Marcello Raimondi¹; Simone Saracino¹; Mukesh Chugh²; Marc Erickson²; Cristian Macario²; Giuseppe Ridinò²
¹ STMicroelectronics; ² MathWorks
A Novel Approach to Functional Test Development and Execution using High-Speed IO
Marcus Schulze Westenhorst¹; Jörg Simon²; Markus Bücker¹; Klaus-Dieter Hilliges¹; Michael Braun¹
¹ Advantest Europe GmbH; ² Cadence Design Systems
Testbench Flexibility as a Foundation for Success
Ana Sanz Carretero¹; Katherine Garden; WeiWei Cheong
¹ Xilinx
Handling Asynchronous Reset(s) Testing by Building Reset-awareness into UVM Testbench Components
Wei Wei Cheong; Katherine Garden; Ana Sanz Carretero
Xilinx Inc.
One Testbench to Rule Them All!
Salman Tanvir; Markus Brosch; Amer Siddiqi
A Comparison of Methodologies to Simulate Mixed-signal IC
Simone Fontanesi¹; Paul Ehrlich²; Karsten Einwich²; Gaetano Formato¹; Andrea Possemato¹
¹ Infineon Technologies Austria AG; ² COSEDA Technologies GmbH
Unified Model/Hardware-in-the-Loop Methodology for Mixed-Signal System Design and Hardware Prototyping
Martin Barnasconi¹; Wil Kitzen¹; Thieu Lammers¹; Paul Ehrlich²; Karsten Einwich²
¹ NXP Semiconductors; ² COSEDA Technologies GmbH
Accelerated Coverage Closure by Utilizing Local Structure in the RTL Code
Gokce Sarar¹; Guillaume Shippee¹; Tushit Jain¹; Rhys Buggy²; Vishal Karna¹; Han Nuon¹
¹ Qualcomm Technologies, Inc.; ² QT Technologies Ireland Limited
Machine Learning based Structure Recognition in Analog Schematics for Constraints Generation
Rituj Patel; PhD Husni Habal; Venkata Konda Reddy Rolla
Democratizing Formal Verification
Tobias Ludwig
Lubis EDA
Netlist Paths: A Tool for Front-end Netlist Analysis
PhD Jamie Hanlon; Samuel Kong
Graphcore Ltd
A Novel Approach to In-System SRAM Repair Verification in Embedded SoC to Bridge Gap between Test and Functional Mode
Harshal Kothari; Eldin Ben Jacob; Sriram Kazhiyur Sounderrajan; Somasunder Kattepura Sreenath
Samsung Semiconductor India R&D
Advance Approach for Formal Verification of Configurable Pulse Width Modulation Controller
Sumit Kumar Kulshreshtha; Raghavendra JN
Intel Technology India Pvt Ltd
An Analysis of Stimulus Techniques for Efficient Functional Coverage Closure
Caglayan Yalcin; Aileen McCabe
QUALCOMM
Centralized Regression Optimisation Toolkit (CROT) for Expediting Regression Closure with Simulator Performance Optimisation
Harshal Kothari; Pavan M; Eldin Ben Jacob; Sriram Kazhiyur Sounderrajan; Somasunder Kattepura Sreenath
Samsung Semiconductor India R&D
Chip-Level Analog Regression in Production
PhD Yi Wang
Dialog Semiconductor B.V.
Emulation Based Power and Performance Workloads on ML NPUs
Pragati Mishra¹; Ritu Suresh; Issac Zacharia; Jitendra Aggarwal
¹ Arm Ltd
Five Ways to Make Your Specman Environment More Reusable and Configurable
Stefan Sljukic; Nikola Knezevic; Filip Dojcinovic
Veriest Solutions
Formal Property Verification of the Digital Section of an Ultra-Low Current Digitizer ASIC
Katharina Ceesay-Seitz¹; Sarath Kundumattathil Mohanan; PhD Hamza Boukabache; Daniel Perrin
¹ CERN
Language-Agnostic Communication for SystemC/TLM-2.0 Compliant Virtual Prototypes
Smruti Khire; Kunal Sharma; Vishal Chovatiya
Infineon Technologies
Maximize PSS Reuse with Unified Test Realization Layer Across Verification Environments
Simranjit Singh¹; Arun K.R.; Ashwani Aggarwal; Suman Kumar Reddy Mekala; Woojoo Space Kim²; Seonil Brian Choi²; Gnaneshwara Tatuskar³
¹ Samsung Semiconductor India R&D; ² Samsung Electronics; ³ Cadence Design Systems
Resetting RDC Expectations – A Systematic Approach to Verifying Complex Configurable Designs
Eamonn Quigley¹; Jonathan Niven¹; Mark Handover²
¹ ARM; ² Siemens
Successive Refinement – An approach to Decouple Front-End and Back-end Power Intent
Rohit Sinha
Intel
Virtual Prototyping of Power Converter Systems Based on AURIX™ using SystemC AMS
Radovan Vuletic¹; Thomas Arndt²; Dineshkumar Selvaraj¹
¹ Infineon Technologies AG; ² COSEDA Technologies GmbH
