DVCon Europe 2023 Recipients
Best Engineering Paper
The Three Body Problem: There’s more to building Silicon than what EDA tools currently help with
Authors: Peter Birch¹; Ben Marshall²
¹ VyperCore; ² PQShield
Best Research Paper
Clock Tree Design Considerations in The Presence of Asymmetric Transistor Aging
Authors: Prof. Dr. Freddy Gabbay PhD¹; Firas Ramadan²; Majd Ganaiem²
¹ Ruppin Academic Center, Israel; ² Technion – Israel Institute of Technology
DVCon Europe 2022 Recipients
Best Paper
A Generic Configurable Error Injection Agent for On-Chip Memories
Authors: Anil Deshpande – Samsung Semiconductor India R & D Centre(SSIR)
Niharika Sachdeva – Samsung Semiconductor India R & D Centre(SSIR)
Arjun Suresh Kumar – Samsung Semiconductor India R & D Centre(SSIR)
Damandeep Saini – Samsung Semiconductor India R & D Centre(SSIR)
Ravi Teja Gopagiri – Samsung Semiconductor India R & D Centre(SSIR)
Somasunder KS – Samsung Semiconductor India R & D Centre(SSIR)
Jaechul Park – Samsung Electronics, Korea
Best Poster
A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development
Authors: Harshal Kothari
Vinay Swargam
Sriram Kazhiyur Sounderrajan
Somasunder Kattepura Sreenath
DVCon Europe 2021 Recipients
Best Paper
Testbench Flexibility as a Foundation for Success
Authors: Ana Sanz Carretero – Xilinx
Katherine Garden – Xilinx
Wei Wei Cheong – Xilinx
Best Poster
An Analysis of Stimulus Techniques for Efficient Functional Coverage Closure
Authors: Caglayan Yalcin – Qualcomm
Aileen McCabe – Qualcomm
DVCon Europe 2020 Recipients
Best Paper
Clock Controller Unit Design Metrics: Area, Power, Software flexibility and Congestion Impacts at System Level
Authors: Michele Chilla – Qualcomm
Leonardo Gobbi – Qualcomm
Best Poster
Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing”
Authors: Ping Yeung – Siemens
Mark Handover – Siemens
Abdel Ayari – Siemens
DVCon Europe 2019 Recipient
Best Paper
5.2 Portable Stimuli Over UVM, Using Portable Stimuli in HW Verification Flow
Authors: Efrat Shneydor – Cadence Design Systems, Inc.
Slava Salnikov – Ben-Gurion University & Bengal Engineering & Science University
Liran Kosovizer – Texas Instruments
Shlomo Greenberg – Ben Gurion University
DVCon Europe 2018 Recipient
Best Paper
12.1: Using Constraints for SystemC AMS Design and Verification
Authors: Thilo Vörtler, Karsten Einwich – COSEDA Technologies
Muhammad Hassan – DFKI
Daniel Grosse – University of Bremen & DFKI GmbH
DVCon Europe 2017 Recipient
Best Paper
3.2: Between the Dialog and the Algorithm or Innovative Technological Narratives Leveraging the Idea of Authenticity in a Human Being
Authors: Hagai Arbel, Anna M. Ravitzki, and Uri Feigin – Vtool Ltd
DVCon Europe 2016 Recipient
Best Paper
6.3: Complete Formal Verification of a Family of Automotive DSPs
Authors: Rafal A. Baranowski & Marco Trunzer – Robert Bosch GmbH
DVCon Europe 2015 Recipients
Best Paper
TA1.1: Is Your Testing N-wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus
Authors: Jonathan Bromley, Kevin Johnston – Verilab
Best Poster
P1.4: UVM and Emulation: How To Get Your Ultimate Testbench Acceleration Speed-up
Authors: Ahmed Yehia, Hans Van der Schoot – Mentor Graphics
DVCon Europe 2014 Recipients
Best Paper
UVM Ready: Transitioning Mixed-Signal Verification Environments to Universal Verification Methodology
Author: Arthur Freitas – Freescale Semiconductor
Best Poster
Understanding the Effectiveness of your System-Level SoC Stimulus Suite
Author: Robert Fredieu – Mentor Graphics
